(1) Field of the Invention
The present invention relates to a heterojunction bipolar transistor comprising different kinds of joined semiconductors, and a manufacturing method thereof.
(2) Description of the Prior Art
A heterojunction bipolar transistor (HBT) is a transistor for use in compound semiconductor integrated circuits. As an exemplary device structure of the HBT, FIG. 1 shows a structure of an npn-type HBT with its emitter on the top, and FIGS. 2a to 2f illustrate manufacturing steps thereof.
In the first place, as shown in FIG. 2a, subcollector layer 102, collector layer 103, base layer 105, and emitter layer 106 are sequentially formed on insulating substrate 101 by using an epitaxial growth method or the like. Then, a metal film which is to serve as emitter electrode 113, later described, is deposited over the entire surface thereof.
Next, as shown in FIG. 2b, photoresist 10 of a predetermined pattern is formed on the metal film and used as a mask to process the metal film, thereby providing emitter electrode 113. Then, photoresist 10 and emitter electrode 113 are used as a mask to remove emitter layer 106 until the surface of base layer 105 is exposed as shown in FIG. 2c. 
Subsequently, photoresist 10 is removed, and a new photoresist mask of a predetermined pattern is formed on the exposed surface of base layer 105 and used to form base electrode 112 as shown in FIG. 2d through vapor deposition and lift-off procedures. Next, as shown in FIG. 2e, photoresist 11 of a predetermined pattern is formed and used as a mask to remove collector layer 103 until the surface of subcollector layer 102 is exposed.
Then, photoresist 11 is removed and photoresist 12 of a predetermined pattern is formed and used as a mask to inject a predetermined impurity into subcollector layer 102 with an ion implantation technique, thereby forming insulating injection area 114 as shown in FIG. 2f. 
Finally, photoresist 12 is removed, a photoresist of a predetermined pattern is formed on the exposed surface of subcollector layer 102 and used as a mask to form collector electrode 111 through vapor deposition and lift-off procedures, thereby obtaining the npn-type HBT device in FIG. 1.
In the aforementioned npn-type HBT, since the junction area (SBC) between base layer 105 and collector layer 103 is larger than the junction area (SBE) between emitter layer 106 and base layer 105, offset voltage occurs in a three-terminal I-V characteristic as shown in FIG. 3. In FIG. 3, the vertical axis represents collector current IC(A) while the horizontal axis represents voltage VCE(V) between the collector and the emitter. The offset voltage shown in FIG. 3 also occurs on conditions as described below.
FIG. 4 is a diagram showing energy bands in an HBT. In the example, difference xcex94EBC (=Egcxe2x88x92Egb) between the band gap (Egb) of base layer 302 and the band gap (Egc) of collector layer 303 is smaller than difference xcex94EBE (=Egexe2x88x92Egb) between the band gap (Ege) of emitter layer 301 and the band gap (Egb) of base layer 302. The offset voltage occurs when xcex94EBC less than xcex94EBE as in the example.
When the aforementioned offset voltage is large, power consumption is greater in a digital IC using an HTB, or power added efficiency is lower in a power amplifier using an HBT, for example.
To avoid the problems, several device structures have been proposed for reducing the offset voltage. As an example, FIG. 5 shows a cross-sectional structure of an HBT which achieves a reduction in offset voltage. The HBT includes collector layer insulation area 131 obtained by insulating the portion of collector layer 103 in the aforementioned HBT shown in FIG. 1 which is joined to an outward base area (an area adjacent to an inward base area directly below the emitter layer) of base layer 105. The provision of collector layer insulation area 131 in collector layer 103 in this manner can reduce the junction area (SBC) between base layer 105 and collector layer 103 to achieve a reduction in the offset voltage.
A structure capable of reducing the offset voltage without using ion implantation is a DHBT (Double Heterojunction Bipolar Transistor). FIG. 6 shows a cross-sectional structure of such a DHBT. The HBT includes collector layer 141 using a semiconductor with a wide energy band gap instead of collector layer 103 in the structure of the aforementioned HBT shown in FIG. 1. With the structure, xcex94EBE can be equal to xcex94EBC to allow a reduction in the offset voltage.
The aforementioned structures of the respective HBTs capable of reducing the offset voltage, however, present problems as below.
In the structure of the HBT shown in FIG. 5, since collector layer insulation area 131 is formed by ion-implanting an impurity into the portion joined to the outward base area close to a device intrinsic area, it is conceivable that the impurity can be diffused to the device intrinsic area. Such diffusion of the impurity to the device intrinsic area brings about a lower current gain in an HTPT test (high temperature passage test) to contribute to reduce reliability of the device.
In the structure of the DHBT shown in FIG. 6, xcex94EBE is equal to xcex94EBC and thus xcex94EBC causes carriers in operation of the device to be blocked, thereby presenting a problem of reducing collector injection efficiency.
It is an object of the present invention to provide a heterojunction bipolar transistor capable of solving the aforementioned problems, providing high reliability of a device, and reducing offset voltage without reducing collector injection efficiency, and a manufacturing method thereof.
To achieve the aforementioned object, a heterojunction bipolar transistor of the present invention comprises a collector layer, a base layer, and an emitter layer stacked sequentially, wherein the base layer comprises a first base layer joined to the collector layer in an inward base area directly below the emitter layer and a second base layer joined to the collector layer in an outward base area adjacent to the inward base area. The second base layer is formed of a semiconductor with a wider energy band gap than the collector layer.
A method of manufacturing a heterojunction bipolar transistor comprises a first step of sequentially stacking a collector layer, a first base layer, and an emitter layer, a second step of removing the first base layer in an outward base area adjacent to an inward base area directly below the emitter layer and a portion of the collector layer directly below the outward base area, and a third step of forming an insulating film made of a predetermined material on the entire surface of the inward base area to sequentially form a second base layer made of a semiconductor with a wider energy band gap than the collector layer and the first base layer on the collector layer from which the portion has been removed in the second step through selective re-growth by using the insulating film.
Another method of manufacturing a heterojunction bipolar transistor comprises a first step of sequentially stacking a collector layer and a first base layer made of a semiconductor with a wider energy band gap than the collector, a second step of forming an insulating film made of a predetermined material on the entire surface of the first base layer and removing the first base layer in an inward base area directly below an emitter layer to be formed on the first base layer and the insulating film on the inward base area to expose a surface of the collector layer, a third step of re-growing a second collector layer on the surface of the collector layer exposed in the second step, and a fourth step of removing the insulating film and then sequentially forming a second base layer made of a predetermined material and the emitter layer made of a semiconductor with a wider energy band gap than the second base layer through re-growth.
As described above, in the present invention, since the energy band gap of the second base layer joined to the collector layer in the outward base area is wider than that of the collector layer, the second base layer suppresses current injection from the collector layer in the junction. In this case, the occurrence of offset voltage is determined by the relationship between the junction area (SBE) between the emitter layer and the first base layer and the junction area (SBC) between the first base layer and the collector layer. In this manner, in the present invention, the junction area (SBC) can be reduced by the provision of the second base layer in the outward base area. Thus, the junction area (SBE) can be substantially the same size as the junction area (SBC).
According to the present invention, the difference in band gaps between the second base layer and the collector layer joined to each other in the outward base area can be larger than the difference in band gaps between the first base layer and the emitter layer joined to each other in the inward base area. with this configuration, collector current in the outward base area is reduced.
In addition, according to the present invention, since a semiconductor of the same material system is used for the first base layer and the collector layer joined to each other in the inward device area, collector injection efficiency is not reduced due to the wide band gap in these layers.
Furthermore, according to the present invention, a material with a wide band gap is used for the second base layer in the outward base area in contact with a base electrode, thereby causing no increase in contact resistance.
As described above, according to the present invention, since ion implantation is not performed near a device intrinsic area, reduced device reliability as conventional is not found. In addition, the use of a semiconductor with a wide band gap only in the outward base area results in no reduction in collector injection efficiency.